In order to generate a voltage lower or higher than a given input voltage, a power circuit such as a DC/DC converter (switching regulator) is used. The power circuit includes an analog control-type power circuit and a digital control-type power circuit. In the analog control-type power circuit, an error between an output voltage of the power circuit and a target value of the power circuit is amplified by an error amplifier, and then a duty ratio of switching is controlled depending on an output of the error amplifier, thereby stabilizing the output voltage to the target vale. In the digital control-type power circuit, an output voltage of the power circuit is converted into a digital value by an A/D converter, and then a duty ratio of a switching transistor is controlled through digital signal processing.
The digital control-type power circuit (digital control power circuit) is not greatly restricted in a control algorithm, so that a degree of freedom of design is high, and there is also advantage that a control scheme or a set value of an output voltage can be changed by software. Further, there is an advantage that can hold the history of various types of data as digital values on the occasion of a long-term operation.
FIG. 1 is a block diagram of a digital control power circuit. A power circuit 100r includes an output circuit 102 and a control circuit 200r. The output circuit 102 includes a switching transistor M1, an inductor L1, a rectifying device D1, and an output capacitor C1.
An A/D converter 202 converts a feedback voltage VFB corresponding to an output voltage VOUT into a digital feedback value DFB. An error detector 212 of a feedback controller 210 generates an error signal DERR indicating an error between the digital feedback value DFB and a target value DREF. A compensator 214 generates a duty command value DDUTY which is changed such that the error signal DERR is close to zero. A pulse generator 220 generates a pulse signal SPWM having a duty ratio corresponding to the duty command value DDUTY. A driver 230 switches the switching transistor M1 depending on the pulse signal SPWM.
FIG. 2 is an operational waveform view of the power circuit 100r of FIG. 1. When a load current IOUT is rapidly increased at a time t1, the charge of an output capacitor C1 is discharged, so that the output voltage VOUT is reduced. There is a delay τ1 until the variation in the output voltage VOUT appears in a sampled feedback value DFB. Further, when the variation in the output voltage VOUT appears in the feedback value DFB, the error signal DERR is increased, but there is a calculation delay τ2 until the error signal DERR is reflected into a duty ratio of the pulse signal SPWM. In addition, due to a delay (not shown in FIG. 2) of the compensator 214, the duty ratio follows the error signal DERR later.
In this manner, since the power circuit 100r samples the output voltage VOUT at a predetermined sampling rate, the power circuit 100r is discontinuously controlled and may have low responsiveness compared with an analog control power circuit which does not require sampling and thus can be continuously controlled. In the example of FIG. 2, after the feedback voltage VFB is lowered, the duty ratio is finally varied at a third pulse P3. That is, there is a great response delay τDELAY, which cannot be neglected, from a time at which the feedback voltage VFB varies to a time at which the duty ratio of the pulse signal SPWM increases, and thus, a variation in the output voltage VOUT is increased.